Package carrier, semiconductor package, and process for fabricating same

ABSTRACT

A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.61/251,396, filed on Oct. 14, 2009, U.S. Provisional Application No.61/294,519, filed on Jan. 13, 2010, and Taiwan Application No. 99112317,filed on Apr. 20, 2010, the disclosures of which are incorporated hereinby reference in their entirety.

FIELD OF THE INVENTION

The present invention relates to a semiconductor package. Moreparticularly, the present invention relates to a package carrier, apackage structure, and a process for fabricating a package carrier and apackage structure.

BACKGROUND

A chip package serves to protect a bare chip, reduce a density of chipcontacts, and provide a good heat dissipation effect for the chip. Acommon packaging process is to install the chip onto a package carrier,and contacts of the chip are electrically connected to the packagecarrier. Therefore, distribution of the contacts of the chip can berearranged through the package carrier to cope with a contactdistribution of a next stage external device.

As light weight, compactness, and high efficiency have become typicalrequirements of consumer electronic and communication products, chippackages should provide superior electrical properties, small overallvolume, and a large number of I/O ports. Package carriers used in thesechip packages often have multiple metal layers that can be electricallyconnected through interconnections. As the size of chip packagesdecreases, these interconnections can become smaller and more closelyspaced, which can increase the cost and complexity of packagingprocesses.

It is against this background that a need arose to develop the packagecarriers, the package structures, and processes described herein.

SUMMARY

In an embodiment, a package carrier includes: (1) a dielectric layerhaving a plurality of openings; (2) a first conductive pattern, disposedadjacent to a first surface of the dielectric layer, the firstconductive pattern including a plurality of first pads; and (3) aplurality of conductive vias disposed in respective ones of theopenings, wherein each conductive via includes a first via segment,connected to at least one of the first pads, and a second via segment,connected to the first via segment, such that a lateral extent of thefirst via segment is different from a lateral extent of the second viasegment.

In another embodiment, a semiconductor package includes: (1) a packagecarrier, including: a dielectric layer; a top conductive pattern,disposed adjacent to a top surface of the dielectric layer, andincluding a plurality of first pads; a bottom conductive pattern,disposed adjacent to a bottom surface of the dielectric layer, andincluding a plurality of second pads; a plurality of conductive vias,embedded in the dielectric layer and extending between the topconductive pattern and the bottom conductive pattern, wherein eachconductive via includes a first segment, connected to at least one ofthe first pads, and a second segment, connected to at least one of thesecond pads; and (2) a chip, attached to the package carrier andconnected to the first pads.

In a further embodiment, a semiconductor fabrication process includes:(1) forming a first conductive pattern including a plurality of firstpads; (2) forming a plurality of first via segments on at least some ofthe first pads; (3) providing a dielectric layer having a plurality offirst openings corresponding to the first via segments; (4) applying thedielectric layer to the first conductive pattern and the first viasegments; (5) forming a plurality of second openings in the dielectriclayer, such that the first via segments are exposed by the secondopenings; and (6) forming a plurality of second via segments on thefirst via segments and at least partially within the second openings,such that a diameter of the first via segment is different than adiameter of the second via segment.

Other aspects and embodiments of the invention are also contemplated.The foregoing summary and the following detailed description are notmeant to restrict the invention to any particular embodiment but aremerely meant to describe some embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the nature and objects of some embodimentsof the invention, reference should be made to the following detaileddescription taken in conjunction with the accompanying drawings. In thedrawings, like reference numbers denote like elements, unless thecontext clearly dictates otherwise.

FIG. 1A through FIG. 1H are cross-sectional views of semiconductorpackages according to various embodiments of the invention.

FIG. 2-1 through FIG. 2-10 illustrate a process for fabricating apackage carrier according to an embodiment of the invention.

FIG. 3-1 through FIG. 3-10 illustrate a process for fabricating apackage carrier according to another embodiment of the invention.

DETAILED DESCRIPTION

FIG. 1A is a cross-sectional view of a semiconductor package 10 aaccording to an embodiment of the invention. Referring to FIG. 1A, thepackage 10 a includes a package carrier 100 a (or other substrate), aset of solder balls 102 (or other electrically conductive bumps), a chip104 (or other active or passive semiconductor device), a set of bondingwires 106, and an encapsulant 108.

In particular, the package carrier 100 a includes a dielectric layer110, a first electrically conductive pattern 120, a set of firstelectrically conductive vias, a second electrically conductive pattern140, a first solder mask layer 150, and a second solder mask layer 160.In the illustrated embodiment, the first conductive vias correspond tofirst electrically conductive posts 130, although pillars and otherhollow or solid structures can be used. The dielectric layer 110includes a first surface 112 and a second surface 114 opposite to thefirst surface 112. The first electrically conductive pattern 120 isembedded within the dielectric layer 110 adjacent to the first surface112 of the dielectric layer 110, and includes a set of first pads 122.Here, the first electrically conductive pattern 120 can be regarded asan embedded circuit, and an exposed surface (e.g., a top surface) of thefirst electrically conductive pattern 120 is aligned (e.g.,substantially aligned) with the first surface 112 of the dielectriclayer 110. The dielectric layer 110 can include a resin material, suchas ammonium bifluoride, ajinomoto build-up film (ABF), bismaleimidetriazine (BT), polyimide (PI), liquid crystal polymer (LCP), epoxyresin, or a combination thereof. These resin materials can be mixed withglass fibers, such as in the form of a fiber pad or other types offibers to strengthen the dielectric layer 110. The first electricallyconductive pattern 120 and the second electrically conductive pattern140 can include a metal, a metal alloy, or other electrically conductivematerial.

The first electrically conductive posts 130 extend through thedielectric layer 110, wherein each of the first electrically conductiveposts 130 includes a first electrically conductive post segment 132 (or,more generally, a first via segment) connected to a corresponding firstpad 122 and a second electrically conductive post segment 134 (or, moregenerally, a second via segment) connected to the first electricallyconductive post segment 132. In the present embodiment, a patternedetching stop layer 180 (or other barrier layer) is located between thefirst electrically conductive post segments 132 and the first pads 122,wherein the first electrically conductive posts 130 can be connected tothe first electrically conductive pattern 120 through the patternedetching stop layer 180 that is formed of, for example, nickel,palladium, or another electrically conductive material. Also, a diameter(or other characteristic lateral extent) of the first electricallyconductive post segment 132 is greater than that of the secondelectrically conductive post segment 134. This difference in diameterbetween the first electrically conductive post segment 132 and thesecond electrically conductive post segment 134 results in that each ofthe first electrically conductive posts 130 includes a larger top orhead part. Advantageously, this difference in diameter and the patternedetching stop layer 180 enhance structural rigidity and reliability ofthe package carrier 100 a by, for example, serving as a lockingmechanism for the first electrically conductive posts 130 with respectto the dielectric layer 110 and, thereby, increasing the degree ofcoupling for the first electrically conductive pattern 120 and thesecond electrically conductive pattern 140 with respect to one anotherand with respect to the dielectric layer 110. In addition, by formingthe first electrically conductive posts 130 within the dielectric layer110, the stress imparted by external forces, such as attributable tomechanical shock, is compensated for, and the reliability of the package10 a is improved. The first electrically conductive posts 130 caninclude a metal (e.g., copper), a metal alloy, or other electricallyconductive material.

The second electrically conductive pattern 140 is disposed adjacent tothe second surface 114 of the dielectric layer 110, and includes a setof second pads 142 that are connected to respective ones of the secondelectrically conductive post segments 134. The first solder mask layer150 is disposed adjacent to the first surface 112 of the dielectriclayer 110, and defines apertures or openings to expose the first pads122. The second solder mask layer 160 is disposed adjacent to the secondsurface 114 of the dielectric layer 110, and defines apertures oropenings to expose the second pads 142.

The first solder balls 102 are respectively disposed adjacent to thesecond pads 142. The chip 104 is mounted adjacent to the package carrier100 a, and is located adjacent to the first surface 112 of thedielectric layer 110. The bonding wires 106 are connected between thechip 104 and the first pads 122. The encapsulant 108 covers the chip104, the bonding wires 106, and a part of the package carrier 100 a.

In the present embodiment, the package 10 a further includes an adhesionlayer 109. The adhesion layer 109 is disposed between the chip 104 andthe first solder mask layer 150 for adhering the chip 104 to the packagecarrier 100 a.

FIG. 1B is a cross-sectional view of a package 10 b according to anotherembodiment of the invention. Referring to FIG. 1A and FIG. 1B, thepackage 10 b of FIG. 1B is similar to the package 10 a of FIG. 1A, andat least one difference is that the adhesion layer 109 of the package 10b of FIG. 1B is disposed between the chip 104 and the first electricallyconductive pattern 120, which is exposed by the first solder mask layer150 of a package carrier 100 b.

FIG. 1C is a cross-sectional view of a package 10 c according to anotherembodiment of the invention. Referring to FIG. 1A and FIG. 1C, thepackage 10 c of FIG. 1C is similar to the package 10 a of FIG. 1A, andat least one difference is that, in a package carrier 100 c of FIG. 1C,the diameter of the first electrically conductive post segment 132 a issmaller than the diameter of the second electrically conductive postsegment 134 a.

FIG. 1D is a cross-sectional view of a package 10 d according to anotherembodiment of the invention. Referring to FIG. 1C and FIG. 1D, thepackage 10 d of FIG. 1D is similar to the package 10 c of FIG. 1C, andat least one difference is that the adhesion layer 109 of the package 10d of FIG. 1D is disposed between the chip 104 and the first electricallyconductive pattern 120, which is exposed by the first solder mask layer150 of a package carrier 100 d.

FIG. 1E is a cross-sectional view of a package 10 e according to anotherembodiment of the invention. Referring to FIG. 1A and FIG. 1E, thepackage 10 e of FIG. 1E is similar to the package 10 a of FIG. 1A, andat least one difference is that a package carrier 100 e of the package10 e of FIG. 1E further includes a chip pad support 170, which caninclude a metal (e.g., copper), a metal alloy, or other electricallyconductive material. The chip pad support 170 extends through thedielectric layer 110, wherein the first electrically conductive pattern120 includes a third pad 124 serving as a chip pad, and the chip 104 ismounted adjacent to the third pad 124. The chip pad support 170 includesa first support segment 172 connected to the third pad 124, and a secondsupport segment 174 connected to the first support segment 172. Thesecond electrically conductive pattern 140 includes a fourth pad 144connected to the second support segment 174. The chip 104 can beconnected to the third pad 124, such as by wire-bonding, and the thirdpad 124 and the chip pad support 170 can provide an electrically pathwaybetween the chip 104 and the fourth pad 144.

In the present embodiment, a diameter of the first support segment 172is greater than that of the second support segment 174. Moreover, thediameter of the first support segment 172 is greater than that of thefirst electrically conductive post segment 132, and the diameter of thesecond support segment 174 is greater than that of the secondelectrically conductive post segment 134. Moreover, the package 10 e ofFIG. 1E further includes a set of second solder balls 103 (or otherelectrically conductive bumps) respectively disposed adjacent to thefourth pad 144.

FIG. 1F is a cross-sectional view of a package 10 f according to anotherembodiment of the invention. Referring to FIG. 1E and FIG. 1F, thepackage 10 f of FIG. 1F is similar to the package 10 e of FIG. 1E, andat least one difference is that the adhesion layer 109 of the package 10f of FIG. 1F is disposed between the chip 104 and the first electricallyconductive pattern 120, which is exposed by the first solder mask layer150 of a package carrier 100 f. In the present embodiment, the adhesionlayer 109 is directly connected to the third pad 124 of the firstelectrically conductive pattern 120.

FIG. 1G is a cross-sectional view of a package 10 g according to anotherembodiment of the invention. Referring to FIG. 1E and FIG. 1G, thepackage 10 g of FIG. 1G is similar to the package 10 e of FIG. 1E, andat least one difference is that, in a package carrier 100 g of FIG. 1G,the diameter of the first support segment 172 a is smaller than that ofthe second support segment 174 a.

FIG. 1H is a cross-sectional view of a package 10 h according to anotherembodiment of the invention. Referring to FIG. 1G and FIG. 1H, thepackage 10 h of FIG. 1H is similar to the package 10 g of FIG. 1G, andat least one difference is that the adhesion layer 109 of the package 10h of FIG. 1H is disposed between the chip 104 and the first electricallyconductive pattern 120, which is exposed by the first solder mask layer150 of a package carrier 100 h. In the present embodiment, the adhesionlayer 109 is directly connected to the third pad 124 of the firstelectrically conductive pattern 120.

In some embodiments, a surface finishing or passivation layer (notshown) can be disposed adjacent to an exposed surface of an electricallyconductive pattern, which layer can include nickel/gold,nickel/cadmium/gold, nickel/silver, gold, tin, alloys thereof (e.g., atin-lead alloy), silver, electroless nickel electroless palladiumimmersion gold (ENEPIG), or a combination thereof.

Although the chip 104 in the aforementioned embodiments is electricallyconnected to the first electrically conductive pattern 120 through awire-bonding technique, the chip 104 can also be electrically connectedto the first electrically conductive pattern 120 through a flip-chipbonding technique, such as by having an exposed surface of the firstelectrically conductive pattern 120 located below the chip 104. Inparticular, the chip 104 can be connected to the exposed surface of thefirst electrically conductive pattern 120 through conductive bumps, suchas solder bumps, copper pillars, copper stud bumps, or golden studbumps. Moreover, an underfill material can be disposed between the chip104 and a package carrier for encapsulating or wrapping the conductivebumps.

Attention next turns to FIG. 2-1 to FIG. 2-10, which illustrate aprocess for fabricating a package carrier according to an embodiment ofthe invention. Referring to FIG. 2-1, a carrier 202, an initialelectrically conductive layer 204, a first electrically conductivepattern 206, and a set of first electrically conductive post segments208 a are provided, wherein the initial electrically conductive layer204 is disposed adjacent to the carrier 202, the first electricallyconductive pattern 206 is disposed adjacent to the initial electricallyconductive layer 204 and includes a set of first pads 206 a, and thefirst electrically conductive post segments 208 a are respectivelydisposed adjacent to the first pads 206 a. As discussed above, apatterned etching stop layer (or other barrier layer) can be locatedbetween the first electrically conductive post segments 208 a and thefirst pads 206 a. In the present embodiment, a semi-additive process canbe used to sequentially form the first electrically conductive pattern206 and the first electrically conductive post segments 208 a adjacentto the initial electrically conductive layer 204.

In particular, a temporary mask of a dielectric material, a photoresist,or other suitable material is disposed adjacent to the initialelectrically conductive layer 204, and then the mask is patterned toform openings at corresponding positions of the first electricallyconductive pattern 206. The initial electrically conductive layer 204 isused as a plating layer, which provides a current pathway to form thefirst electrically conductive pattern 206 in the openings throughelectroplating. Then, the mask used for the electroplating is removed.

Then, a temporary mask of a dielectric material, a photoresist, or othersuitable material is disposed adjacent to the first electricallyconductive pattern 206 and the initial electrically conductive layer204. Then, the mask is patterned to form openings at correspondingpositions of the first electrically conductive post segments 208 a. Thefirst electrically conductive pattern 206 and the initial electricallyconductive layer 204 are used as plating layers, which provide a currentpathway to form the first electrically conductive post segments 208 a inthe openings through electroplating. Then, the mask used for theelectroplating is removed.

Next, referring to FIG. 2-2, a dielectric layer 210 is provided, whereinthe dielectric layer 210 is pre-formed with a set of first openings 210a, and positions of the first openings 210 a respectively correspond topositions of the first electrically conductive post segments 208 a. Inthe present embodiment, the dielectric layer 210 can be afiber-reinforced resin material, such as a prepreg material. While theopenings 210 a are shown in FIG. 2-2 as fully extending through thedielectric layer 210, it is contemplated that the openings 210 a alsocan partially extend through the dielectric layer 210.

Then, referring to FIG. 2-3, the dielectric layer 210 is laminated tothe initial electrically conductive layer 204, so that the firstelectrically conductive pattern 206 and the first electricallyconductive post segments 208 a are embedded in the dielectric layer 210.In the case where the openings 210 a (shown in FIG. 2-2) fully extendthrough the dielectric layer 210, a thermal lamination process can beused, which can result in some dielectric material being displaced so asto cover top ends of the first electrically conductive post segments 208a as shown in FIG. 2-3. It is also contemplated that the dielectriclayer 210 can be formed in situ adjacent to the initial electricallyconductive layer 204.

Then, referring to FIG. 2-4, an electrically conductive layer 211 (e.g.,a metal film or foil) is laminated to the dielectric layer 210, so thatthe dielectric layer 210 is laminated between the electricallyconductive layer 211 and the initial electrically conductive layer 204.In some embodiments, the dielectric layer 210 and the electricallyconductive layer 211 can be simultaneously laminated to the initialelectrically conductive layer 204 in a common process operation.

Next, referring to FIG. 2-5, a set of conformal openings 211 a areformed in the electrically conductive layer 211. The conformal openings211 a respectively expose parts of the dielectric layer 210 at positionscorresponding to the first electrically conductive post segments 208 a.In the present embodiment, a diameter of each of the conformal openings211 a is smaller than a diameter of the corresponding first electricallyconductive post segment 208 a.

Then, referring to FIG. 2-6, the parts of the dielectric layer 210exposed by the conformal openings 211 a are removed to form a set ofsecond openings 210 b in the dielectric layer 210, so that the firstelectrically conductive post segments 208 a are respectively exposed bythe second openings 210 b. In the present embodiment, the electricallyconductive layer 211 can be used as a conformal mask to selectivelyremove the parts of the dielectric layer 210 exposed by the conformalopenings 211 a through plasma etching, so as to form the second openings210 b. Alternatively, or in conjunction, the parts of the dielectriclayer 210 exposed by the conformal openings 211 a can be removed bylaser drilling or another material removal technique. In the presentembodiment, a diameter of each of the second openings 210 b is smallerthan the diameter of the corresponding first electrically conductivepost segment 208 a.

Next, referring to FIG. 2-6 and FIG. 2-7, the electrically conductivelayer 211 is removed to expose the dielectric layer 210.

Then, referring to FIG. 2-8, a second electrically conductive postsegment 208 b is formed in each of the second openings 210 b, whereineach second electrically conductive post segment 208 b and thecorresponding first electrically conductive post segment 208 a areconnected together to form an electrically conductive post 208. In thepresent embodiment, the second electrically conductive post segments 208b can be formed through electroplating. It should be noted that, sincethe diameter of the second opening 210 b is smaller than the diameter ofthe first electrically conductive post segment 208 a, the diameter ofthe second electrically conductive post segment 208 b is smaller thanthat of the first electrically conductive post segment 208 a.

Then, still referring to FIG. 2-8, a second electrically conductivepattern 212 is formed adjacent to the second electrically conductivepost segments 208 b and the dielectric layer 210, wherein the secondelectrically conductive pattern 212 includes a set of second pads 212 a,and the second pads 212 a are respectively connected to the secondelectrically conductive post segments 208 b. In the present embodiment,a non-patterned electrically conductive layer (not shown) is firstformed adjacent to the dielectric layer 210 and the second electricallyconductive post segments 208 b through electroplating, and then thenon-patterned electrically conductive layer is patterned to form thesecond electrically conductive pattern 212. During electroplating toform the non-patterned electrically conductive layer, the secondelectrically conductive post segments 208 b can also be formed in acommon process operation.

Next, referring to FIG. 2-8 and FIG. 2-9, the carrier 202 and theinitial electrically conductive layer 204 are removed. In the presentembodiment, the carrier 202 and the initial electrically conductivelayer 204 can have a release interface in between, so that the carrier202 can be released from the initial electrically conductive layer 204.Moreover, the initial electrically conductive layer 204 can be removedby etching, and exposed surfaces (e.g., of the second electricallyconductive pattern 212) can be protected from etching while the initialelectrically conductive layer 204 is removed.

Next, referring to FIG. 2-10, a first solder mask layer 214 is formedadjacent to the first electrically conductive pattern 206, wherein thefirst solder mask layer 214 exposes the first pads 206 a. Moreover, asecond solder mask layer 216 is formed adjacent to the secondelectrically conductive pattern 212, wherein the second solder masklayer 216 exposes the second pads 212 a. In some embodiments, a surfacefinishing or passivation layer (not shown) can be formed adjacent toeither, or both, of the first pads 206 a and the second pads 212 a. Thesurface passivation layer can include, for example, nickel/gold,nickel/cadmium/gold, nickel/silver, gold, tin, alloys thereof (e.g., atin-lead alloy), silver, electroless nickel electroless palladiumimmersion gold (ENEPIG), or a combination thereof.

Once a package carrier is fabricated in accordance with FIG. 2-1 throughFIG. 2-10, a package according to an embodiment of the invention can befabricated by disposing a chip (e.g., the chip 104 in FIG. 1A) adjacentto the package carrier, electrically connecting the chip to the firstpads 206 a, and disposing solder balls (e.g., the first solder balls 102of FIG. 1A) adjacent to respective ones of the second pads 212 a.

FIG. 3-1 to FIG. 3-10 illustrate a process for fabricating a packagecarrier according to another embodiment of the invention. Referring toFIG. 3-1, a carrier 302, an initial electrically conductive layer 304, afirst electrically conductive pattern 306, and a set of firstelectrically conductive post segments 308 a are provided, wherein theinitial electrically conductive layer 304 is disposed adjacent to thecarrier 302, the first electrically conductive pattern 306 is disposedadjacent to the initial electrically conductive layer 304 and includes aset of first pads 306 a, and the first electrically conductive postsegments 308 a are respectively disposed adjacent to the first pads 306a. In the present embodiment, a semi-additive process can be used tosequentially form the first electrically conductive pattern 306 and thefirst electrically conductive post segments 308 a adjacent to theinitial electrically conductive layer 304.

In particular, a temporary mask of a dielectric material, a photoresist,or other suitable material is disposed adjacent to the initialelectrically conductive layer 304, and then the mask is patterned toform openings at corresponding positions of the first electricallyconductive pattern 306. The initial electrically conductive layer 304 isused as a plating layer, which provides a current pathway to form thefirst electrically conductive pattern 306 in the openings throughelectroplating. Then, the mask used for the electroplating is removed.

Then, a temporary mask of a dielectric material, a photoresist, or othersuitable material is disposed adjacent to the first electricallyconductive pattern 306 and the initial electrically conductive layer304. Then, the mask is patterned to form openings at correspondingpositions of the first electrically conductive post segments 308 a. Thefirst electrically conductive pattern 306 and the initial electricallyconductive layer 304 are used as plating layers, which provide a currentpathway to form the first electrically conductive post segments 308 a inthe openings through electroplating. Then, the mask used for theelectroplating is removed.

Next, referring to FIG. 3-2, a dielectric layer 310 is provided, whereinthe dielectric layer 310 is pre-formed with a set of first openings 310a, and positions of the first openings 310 a respectively correspond topositions of the first electrically conductive post segments 308 a. Inthe present embodiment, the dielectric layer 310 can be afiber-reinforced resin material, such as a prepreg material. While theopenings 310 a are shown in FIG. 3-2 as fully extending through thedielectric layer 310, it is contemplated that the openings 310 a alsocan partially extend through the dielectric layer 310.

Then, referring to FIG. 3-3, the dielectric layer 310 is laminated tothe initial electrically conductive layer 304, so that the firstelectrically conductive pattern 306 and the first electricallyconductive post segments 308 a are embedded in the dielectric layer 310.In the case where the openings 310 a (shown in FIG. 3-2) fully extendthrough the dielectric layer 310, a thermal lamination process can beused, which can result in some dielectric material being displaced so asto cover top ends of the first electrically conductive post segments 308a as shown in FIG. 3-3. It is also contemplated that the dielectriclayer 310 can be formed in situ adjacent to the initial electricallyconductive layer 304.

Then, referring to FIG. 3-4, an electrically conductive layer 311 (e.g.,a metal film or foil) is laminated to the dielectric layer 310, so thatthe dielectric layer 310 is laminated between the electricallyconductive layer 311 and the initial electrically conductive layer 304.In some embodiments, the dielectric layer 310 and the electricallyconductive layer 311 can be simultaneously laminated to the initialelectrically conductive layer 304 in a common process operation.

Next, referring to FIG. 3-5, a set of conformal openings 311 a areformed in the electrically conductive layer 311. The conformal openings311 a respectively expose parts of the dielectric layer 310 at positionscorresponding to the first electrically conductive post segments 308 a.In the present embodiment, a diameter of each of the conformal openings311 a is greater than a diameter of the corresponding first electricallyconductive post segment 308 a.

Then, referring to FIG. 3-6, the parts of the dielectric layer 310exposed by the conformal openings 311 a are removed to form a set ofsecond openings 310 b in the dielectric layer 310, so that the firstelectrically conductive post segments 308 a are respectively exposed bythe second openings 310 b. In the present embodiment, the electricallyconductive layer 311 can be used as a conformal mask to selectivelyremove the parts of the dielectric layer 310 exposed by the conformalopenings 311 a through plasma etching, so as to form the second openings310 b. Alternatively, or in conjunction, the parts of the dielectriclayer 310 exposed by the conformal openings 311 a can be removed bylaser drilling or another material removal technique. In the presentembodiment, a diameter of each of the second openings 310 b is greaterthan the diameter of the corresponding first electrically conductivepost segment 308 a.

Next, referring to FIG. 3-6 and FIG. 3-7, the electrically conductivelayer 311 is removed to expose the dielectric layer 310.

Then, referring to FIG. 3-8, a second electrically conductive postsegment 308 b is formed in each of the second openings 310 b, whereineach second electrically conductive post segment 308 b and thecorresponding first electrically conductive post segment 308 a areconnected together to form an electrically conductive post 308. In thepresent embodiment, the second electrically conductive post segments 308b can be formed through electroplating. It should be noted that, sincethe diameter of the second opening 310 b is greater than the diameter ofthe first electrically conductive post segment 308 a, the diameter ofthe second electrically conductive post segment 308 b is greater thanthat of the first electrically conductive post segment 308 a.

Then, still referring to FIG. 3-8, a second electrically conductivepattern 312 is formed adjacent to the second electrically conductivepost segments 308 b and the dielectric layer 310, wherein the secondelectrically conductive pattern 312 includes a set of second pads 312 a,and the second pads 312 a are respectively connected to the secondelectrically conductive post segments 308 b. In the present embodiment,a non-patterned electrically conductive layer (not shown) is firstformed adjacent to the dielectric layer 310 and the second electricallyconductive post segments 308 b through electroplating, and then thenon-patterned electrically conductive layer is patterned to form thesecond electrically conductive pattern 312. During electroplating toform the non-patterned electrically conductive layer, the secondelectrically conductive post segments 308 b can also be formed in acommon process operation.

Next, referring to FIG. 3-8 and FIG. 3-9, the carrier 302 and theinitial electrically conductive layer 304 are removed. In the presentembodiment, the carrier 302 and the initial electrically conductivelayer 304 can have a release interface in between, so that the carrier302 can be released from the initial electrically conductive layer 304.Moreover, the initial electrically conductive layer 304 can be removedby etching, and exposed surfaces (e.g., of the second electricallyconductive pattern 312) can be protected from etching while the initialelectrically conductive layer 304 is removed.

Next, referring to FIG. 3-10, a first solder mask layer 314 is formedadjacent to the first electrically conductive pattern 306, wherein thefirst solder mask layer 314 exposes the first pads 306 a. Moreover, asecond solder mask layer 316 is formed adjacent to the secondelectrically conductive pattern 312, wherein the second solder masklayer 316 exposes the second pads 312 a. In some embodiments, a surfacefinishing or passivation layer (not shown) can be formed adjacent toeither, or both, of the first pads 306 a and the second pads 312 a. Thesurface passivation layer can include, for example, nickel/gold,nickel/cadmium/gold, nickel/silver, gold, tin, alloys thereof (e.g., atin-lead alloy), silver, electroless nickel electroless palladiumimmersion gold (ENEPIG), or a combination thereof.

Once a package carrier is fabricated in accordance with FIG. 3-1 throughFIG. 3-10, a package according to an embodiment of the invention can befabricated by disposing a chip (e.g., the chip 104 in FIG. 1C) adjacentto the package carrier, electrically connecting the chip to the firstpads 306 a, and disposing solder balls (e.g., the first solder balls 102of FIG. 1C) adjacent to respective ones of the second pads 312 a.

It should be recognized that similar operations as discussed for FIG.2-1 through FIG. 2-10 and FIG. 3-1 through FIG. 3-10 can be used tofabricate a package carrier and a package including a chip pad and achip support pad that is connected to the chip pad (e.g., as illustratedin FIG. 1E through FIG. 1H).

In summary, in a package carrier of some embodiments of the invention,electrically conductive posts can be used so as to effectively reduce apackage size and a package area, while controlling the cost andcomplexity of packaging processes.

While the invention has been described with reference to the specificembodiments thereof, it should be understood by those skilled in the artthat various changes may be made and equivalents may be substitutedwithout departing from the true spirit and scope of the invention. Inaddition, modifications may be made to adapt a particular situation,material, composition of matter, method, or process, within the scope ofthe claims, including variances or tolerances attributable tomanufacturing processes and techniques. In particular, while the methodsdisclosed herein have been described with reference to particularoperations performed in a particular order, it will be understood thatthese operations may be combined, sub-divided, or re-ordered to form anequivalent method and resultant structure consistent with the teachingsof the invention.

1. A package carrier, comprising: a dielectric layer having a pluralityof openings; a first conductive pattern, disposed adjacent to a firstsurface of the dielectric layer, the first conductive pattern includinga plurality of first pads; and a plurality of conductive vias disposedin respective ones of the openings, wherein each conductive via includesa first via segment, connected to at least one of the first pads, and asecond via segment, connected to the first via segment, such that alateral extent of the first via segment is different from a lateralextent of the second via segment.
 2. The package carrier as claimed inclaim 1, wherein the first conductive pattern is embedded in thedielectric layer.
 3. The package carrier as claimed in claim 1, whereinthe lateral extent of the first via segment is greater than the lateralextent of the second via segment.
 4. The package carrier as claimed inclaim 1, wherein the conductive vias provide a locking mechanism withrespect to the dielectric layer.
 5. The package carrier as claimed inclaim 1, further comprising: a second conductive pattern, disposedadjacent to a second surface of the dielectric layer and including aplurality of second pads, wherein the second via segment of eachconductive via is connected to at least one of the second pads.
 6. Thepackage carrier as claimed in claim 5, further comprising: a chip padsupport, extending through the dielectric layer, wherein the firstconductive pattern includes a third pad corresponding to a chip pad, andthe chip pad support includes a first support segment, connected to thechip pad, and a second support segment, connected to the first supportsegment.
 7. The package carrier as claimed in claim 6, wherein thesecond conductive pattern includes a fourth pad connected to the secondsupport segment, a lateral extent of the first support segment isgreater than the lateral extent of the first via segment, and a lateralextent of the second support segment is greater than the lateral extentof the second via segment.
 8. The package carrier as claimed in claim 7,wherein the lateral extent of the first support segment is greater thanthe lateral extent of the second support segment.
 9. The package carrieras claimed in claim 1, further comprising: a chip pad support, extendingthrough the dielectric layer, wherein the first conductive patternincludes a chip pad, and the chip pad support includes a first supportsegment, connected to the chip pad, and a second support segment,connected to the first support segment.
 10. A semiconductor package,comprising: a package carrier, including: a dielectric layer; a topconductive pattern, disposed adjacent to a top surface of the dielectriclayer, and including a plurality of first pads; a bottom conductivepattern, disposed adjacent to a bottom surface of the dielectric layer,and including a plurality of second pads; and a plurality of conductivevias within the dielectric layer and extending between the topconductive pattern and the bottom conductive pattern, wherein eachconductive via includes a first segment, connected to at least one ofthe first pads, and a second segment, connected to at least one of thesecond pads; and a chip, attached to the package carrier and connectedto the first pads.
 11. The semiconductor package as claimed in claim 10,wherein the top conductive pattern is embedded in the dielectric layer.12. The semiconductor package as claimed in claim 10, wherein a lateralextent of the first segment is greater than a lateral extent of thesecond segment.
 13. The semiconductor package as claimed in claim 10,wherein the conductive vias provide a locking mechanism with respect tothe dielectric layer.
 14. The semiconductor package as claimed in claim10, wherein a top surface of the top conductive pattern is aligned withthe top surface of the dielectric layer.
 15. The semiconductor packageas claimed in claim 10, wherein the package carrier further includes: achip pad support, extending through the dielectric layer, wherein thetop conductive pattern includes a third pad corresponding to a chip pad,the chip is disposed adjacent to the chip pad, the chip pad supportincludes a third segment, connected to the chip pad, and a fourthsegment, connected to the third segment, the bottom conductive patternincludes a fourth pad connected to the fourth segment, a lateral extentof the third segment is greater than a lateral extent of the firstsegment, and a lateral extent of the fourth segment is greater than alateral extent of the second segment.
 16. The semiconductor package asclaimed in claim 15, further comprising: at least one conductive bump,disposed adjacent to the fourth pad.
 17. The semiconductor package asclaimed in claim 10, wherein the package carrier further includes: anetching stop layer, disposed between the conductive vias and the topconductive pattern.
 18. The semiconductor package as claimed in claim10, wherein the conductive vias correspond to conductive posts.
 19. Asemiconductor fabrication process, comprising: forming a firstconductive pattern including a plurality of first pads; forming aplurality of first via segments on at least some of the first pads;providing a dielectric layer having a plurality of first openingscorresponding to the first via segments; applying the dielectric layerto the first conductive pattern and the first via segments; forming aplurality of second openings in the dielectric layer, such that thefirst via segments are exposed by the second openings; and forming aplurality of second via segments on the first via segments and at leastpartially within the second openings, such that a diameter of the firstvia segment is different than a diameter of the second via segment. 20.The process as claimed in claim 19, further comprising: forming a secondconductive pattern including a plurality of second pads, wherein thesecond via segments are connected to at least some of the second pads.